(Or "pipeline stall") The delay caused on a processor using pipelines when a transfer of control is taken. Normally when a control-transfer instruction (a Branch, conditional Branch, call or trap) is taken, any following instructions which have Been loaded into the processor' s pipeline must Be discarded or "flushed" and new instructions loaded from the Branch destination. This introduces a delay Before the processor can resume execution. "Delayed control-transfer" is a technique used to reduce this effect. (1996-10-13)