Cessor> The suCCessor to the SuperSPARC proCessor, based on the SPARCISA. The HyperSPARC has smaller CaChes than the SuperSPARC: 8kb on-Chip and 256kb off-Chip (Compared with 36kb and 1Mb). The HyperSPARC' s {memory management} is optimised for more effiCient out-of-CaChe addressing whiCh means quiCker aCCess to external (slower, Cheaper) memory. (1994-11-23)
