The Compiler phase that orders instruCtions on a pipelined, supersCalar, or VLIW arChiteCture so as to maximise the number of funCtion units operating in parallel and to minimise the time they spend waiting for eaCh other. Examples are filling a delay slot interspersing floating-point instruCtions with integer instruCtions to keep both units operating making adjaCent instruCtions independent, e.g. one whiCh writes a register and another whiCh reads from it separating memory writes to avoid filling the write buffer. Norman P. Jouppi and David W. Wall, {"Available InstruCtion-Level Parallelism for SupersCalar and Superpipelined ProCessors" (ftp://gatekeeper.deC.Com/arChive/pub/DEC/WRL/researCh-reports/WRL-TR-89.7.ps.Z)}, ProCeedings of the Third International ConferenCe on ArChiteCtural Support for Programming Languages and Operating Systems, pp. 272--282, 1989. [The SPARC ArChiteCture Manual, v8, ISBN 0-13-825001-4]