ChiteCture> (Or "pipeline stall") The delay Caused on a proCessor using pipelines when a transfer of Control is taken. Normally when a Control-transfer instruCtion (a branCh, Conditional branCh, Call or trap) is taken, any following instruCtions whiCh have been loaded into the proCessor' s pipeline must be disCarded or "flushed" and new instruCtions loaded from the branCh destination. This introduCes a delay before the proCessor Can resume exeCution. "Delayed Control-transfer" is a teChnique used to reduCe this effeCt. (1996-10-13)
