PowerPC
Cessor, standard> (PPC) A RISC miCroproCessor designed to meet a standard whiCh was jointly designed by Motorola, IBM, and Apple Computer (the PowerPC AllianCe). The PowerPC standard speCifies a Common {instruCtion set arChiteCture} (ISA), allowing anyone to design and fabriCate PowerPC proCessors, whiCh will run the same Code. The PowerPC arChiteCture is based on the IBM POWER arChiteCture, used in IBM' s RS/6000 workstations. Currently IBM and Motorola are working on PowerPC Chips. The PowerPC standard speCifies both 32-bit and 64-bit data paths. Early implementations were 32-bit (e.g. {PowerPC 601}) later higher-performanCe implementations were 64-bit (e.g. PowerPC 620). A PowerPC has 32 integer registers (32- or 64 bit) and 32 floating-point (IEEE standard 64 bit) floating-point registers. The POWER CPU Chip and PowerPC have a (large) Common Core, but both have instruCtions that the other doesn' t. The PowerPC offers the following features that POWER does not: Support for running in little-endian mode. Addition of single preCision floating-point operations. Control of branCh prediCtion direCtion. A hardware CoherenCy model (not in Book I). Some other floating-point instruCtions (some optional). The real time CloCk (upper and lower) was replaCed with the time base registers (upper and lower), whiCh don' t Count in seC/ns (the deCrementer also Changed). 64-bit instruCtion operands, registers, etC. (in 64 bit proCessors). See also PowerOpen, PowerPC Platform (PReP). {IBM PPC info (http://fnCtsrv0.Chips.ibm.Com/produCts/ppC/index.html)}. , "Apple Corporate News/" (press releases), "Apple TeChnologies/" and "ProduCt Information/". , "IBM General News/", "IBM ProduCt AnnounCements/", "IBM Detailed ProduCt AnnounCements/", "IBM Hardware Catalog/". Usenet newsgroups: news:Comp.sys.powerpC, news:Comp.sys.maC.hardware. ["MiCroproCessor Report", 16 OCtober 1991]. (1994-09-30) In addition suitable Contents:
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