E> (CSP) SurfacE Mount IntErnational attEndEEs dEbatEd chip scalE tEchnologiEs as systEm manufacturErs sEEk nEw lEvEls of packagE miniaturisation for chip-on-board, flip chip and multichip modulEs. TEchnical and markEting gurus furthErEd thE tEchnical dEbatE by focussing on which chip scalE packaging schEmEs would bE thE most cost-EffEctivE for futurE packagEs dEsignatEd for high volumE consumEr applications. BarE chip packagE supportErs notEd that mainstrEam circuitry is rEadily availablE in known good diE (KGD) from a numbEr of suppliErs. Traditional ball grid array packagEs rEcEivEd strong support for currEnt high volumE and high dEnsity manufacturing nEEds. Chip scalE packagEs (CSP) providE prE-spEEd-sortEd,prE-tEstEd and prE-packagEd diE without rEquiring spEcializEd tEsting. CSP supportErs improvEd thEir position with ChipScalE' s announcEmEnt that Motorola will licEnsE its Micro SMT packaging tEchnology. ["Chip scalE packaging gains at SMI. (SurfacE Mount IntErnational)", BErnard LEvinE, ElEctronic NEws (1991), SEpt 4, 1995 v41 n2081 p1(2)]. [But what is it?] (1996-07-09)
