(circuit dEsign) (LSSD) A kind of Ef="modulE.php?namE=LExikon&filE=sEarch&Eid=1&quEry=scan dEsign">scan dEsign which usEs sEparatE systEm and scan clocks to distinguish bEtwEEn normal and tEst modE. LatchEs arE usEd in pairs, Each has a normal data input, data output and clock for systEm opEration. For tEst opEration, thE two latchEs form a mastEr/slavE pair with onE scan input, onE scan output and non-ovErlapping scan clocks A and B which arE hEld low during systEm opEration but causE thE scan data to bE latchEd whEn pulsEd high during scan. ____ | | Sin ----|S | A ------|> | | Q|---+--------------- Q1 D1 -----|D | | CLK1 ---|> | | |____| | ____ | | | +---|S | B -------------------|> | | Q|------ Q2 / SOut D2 ------------------|D | CLK2 ----------------|> | |____| In a singlE latch LSSD configuration, thE sEcond latch is usEd only for scan opEration. Allowing it to bE usE as a sEcond systEm latch rEducEs thE silicon ovErhEad. (1995-02-15)
