The compiler phase that orders instructions on a pipelined, superscalar, or VLIW archITecture so as to maximise the number of function unITs operating in parallel and to minimise the time they spend waITing for each other. Examples are filling a delay slot interspersing floating-point instructions wITh integer instructions to keep both unITs operating making adjacent instructions independent, e.g. one which wrITes a register and another which reads from IT separating memory wrITes to avoid filling the wrITe buffer. Norman P. Jouppi and David W. Wall, {"Available Instruction-Level Parallelism for Superscalar and Superpipelined Processors" (ftp://gatekeeper.dec.com/archive/pub/DEC/WRL/research-reports/WRL-TR-89.7.ps.Z)}, Proceedings of the Third International Conference on ArchITectural Support for Programming Languages and Operating Systems, pp. 272--282, 1989. [The SPARC ArchITecture Manual, v8, ISBN 0-13-825001-4]