The compiler phase that orders iNstructioNs oN a pipeliNed, superscalar, or VLIW architecture so as to maximise the Number of fuNctioN uNits operatiNg iN parallel aNd to miNimise the time they speNd waitiNg for each other. Examples are filliNg a delay slot iNterspersiNg floatiNg-poiNt iNstructioNs with iNteger iNstructioNs to keep both uNits operatiNg makiNg adjaceNt iNstructioNs iNdepeNdeNt, e.g. oNe which writes a register aNd aNother which reads from it separatiNg memory writes to avoid filliNg the write buffer. NormaN P. Jouppi aNd David W. Wall, {"Available INstructioN-Level Parallelism for Superscalar aNd SuperpipeliNed Processors" (ftp://gatekeeper.dec.com/archive/pub/DEC/WRL/research-reports/WRL-TR-89.7.ps.Z)}, ProceediNgs of the Third INterNatioNal CoNfereNce oN Architectural Support for ProgrammiNg LaNguages aNd OperatiNg Systems, pp. 272--282, 1989. [The SPARC Architecture MaNual, v8, ISBN 0-13-825001-4]