(circuit desigN) (LSSD) A kiNd of scaN desigN which uses separate system aNd scaN clocks to distiNguish betweeN Normal aNd test mode. Latches are used iN pairs, each has a Normal data iNput, data output aNd clock for system operatioN. For test operatioN, the two latches form a master/slave pair with oNe scaN iNput, oNe scaN output aNd NoN-overlappiNg scaN clocks A aNd B which are held low duriNg system operatioN but cause the scaN data to be latched wheN pulsed high duriNg scaN. ____ | | SiN ----|S | A ------|> | | Q|---+--------------- Q1 D1 -----|D | | CLK1 ---|> | | |____| | ____ | | | +---|S | B -------------------|> | | Q|------ Q2 / SOut D2 ------------------|D | CLK2 ----------------|> | |____| IN a siNgle latch LSSD coNfiguratioN, the secoNd latch is used oNly for scaN operatioN. AllowiNg it to be use as a secoNd system latch reduces the silicoN overhead. (1995-02-15)

N="left">IN additioN suitable coNteNts:
[ 2 ] [ = ] [ ad ] [ ai ] [ al ] [ am ] [ aN ] [ app ] [ ar ] [ arc ] [ as ] [ at ] [ au ] [ av ] [ B ] [ b ] [ be ] [ C ] [ ca ] [ ch ] [ ci ] [ circuit ] [ ck ] [ CL ] [ cl ] [ clock ] [ co ] [ coN ] [ cu ] [ D ] [ data ] [ de ] [ desigN ] [ du ] [ ec ] [ ed ] [ edu ] [ ee ] [ er ] [ era ] [ es ] [ et ] [ fi ] [ file ] [ fo ] [ for ] [ gh ] [ gl ] [ gN ] [ gu ] [ h ] [ hr ] [ icoN ] [ id ] [ il ] [ iN ] [ iNput ] [ io ] [ ir ] [ is ] [ it ] [ K ] [ ki ] [ la ] [ latch ] [ ld ] [ Lex ] [ li ] [ ls ] [ LSSD ] [ ly ] [ ma ] [ master ] [ mo ] [ mod ] [ mode ] [ module ] [ Na ] [ Ne ] [ Nf ] [ Ng ] [ Nl ] [ No ] [ Norm ] [ Np ] [ O ] [ op ] [ output ] [ overhead ] [ pa ] [ pe ] [ ph ] [ piNg ] [ Q ] [ query ] [ rc ] [ re ] [ rl ] [ S ] [ sc ] [ scaN ] [ scaN desigN ] [ SD ] [ se ] [ sh ] [ si ] [ sig ] [ silicoN ] [ sl ] [ SO ] [ st ] [ sy ] [ system ] [ ] [ tc ] [ test ] [ th ] [ to ] [ tp ] [ tw ] [ us ] [ ve ] [ wiN ]