register
1. One of a Small number of high- Speed memory location S in a computer' S CPU. Regi Ster S differ from ordinary random acceSS memory in Several re Spect S: There are only a Small number of regi Ster S (the "regi Ster Set"), typically 32 in a modern proce SSor though Some, e.g. SPARC, have a S many a S 144. A regi Ster may be directly addre SSed with a few bit S. In contra St, there are u Sually million S of word S of main memory (RAM), requiring at lea St twenty bit S to Specify a memory location. Main memory location S are often Specified indirectly, u Sing an {indirect addre SSing} mode where the actual memory addre SS i S held in a regi Ster. Regi Ster S are fa St typically, two regi Ster S can be read and a third written -- all in a Single cycle. Memory i S Slower a Single acce SS can require Several cycle S. The limited Size and high Speed of the regi Ster Set make S it one of the critical re Source S in mo St computer architecture S. RegiSter allocation, typically one pha Se of the back-end, control S the u Se of regi Ster S by a compiled program. See al So accumulator, FUBAR, orthogonal, {regi Ster dancing}, {regi Ster allocation}, {regi Ster Spilling}. 2. An addre SSable location in a memory-mapped peripheral device. E.g. the tran Smit data regi Ster in a UART. Style="border-width:thin; border-color:#333333; border-Style:daShed; padding:5px;" align="left">In addition Suitable contentS: [ 2 ] [ = ] [ accumulator ] [ ad ] [ addreSS ] [ ai ] [ al ] [ AM ] [ am ] [ an ] [ app ] [ ar ] [ ARC ] [ arc ] [ architecture ] [ ART ] [ aS ] [ at ] [ av ] [ B ] [ b ] [ ba ] [ back-end ] [ be ] [ bi ] [ bit ] [ by ] [ C ] [ ca ] [ cat ] [ cc ] [ ch ] [ ci ] [ ck ] [ cl ] [ co ] [ com ] [ computer ] [ con ] [ control ] [ CP ] [ CPU ] [ cr ] [ cu ] [ cy ] [ cycle ] [ data ] [ dd ] [ de ] [ device ] [ diff ] [ do ] [ du ] [ E ] [ ec ] [ ed ] [ ee ] [ eg ] [ er ] [ era ] [ eS ] [ et ] [ faS ] [ fi ] [ file ] [ fr ] [ FUBAR ] [ gh ] [ gi ] [ gl ] [ gr ] [ h ] [ hit ] [ hog ] [ hr ] [ id ] [ ie ] [ iff ] [ il ] [ in ] [ indirect addreSS ] [ indirect addreSSing ] [ io ] [ ir ] [ iS ] [ it ] [ ke ] [ la ] [ ld ] [ Lex ] [ li ] [ location ] [ lS ] [ ly ] [ M ] [ ma ] [ main memory ] [ mall ] [ man ] [ map ] [ memory ] [ memory location ] [ mil ] [ mill ] [ mo ] [ mod ] [ mode ] [ module ] [ mp ] [ mu ] [ na ] [ nc ] [ ne ] [ ng ] [ nl ] [ nS ] [ nu ] [ O ] [ om ] [ orthogonal ] [ PARC ] [ pe ] [ peripheral ] [ peripheral device ] [ ph ] [ phaSe ] [ pr ] [ proceSS ] [ proceSSor ] [ program ] [ query ] [ RAM ] [ random ] [ rc ] [ re ] [ regiSter allocation ] [ regiSter dancing ] [ regiSter Set ] [ regiSter Spilling ] [ ro ] [ S ] [ Sa ] [ Se ] [ Set ] [ Si ] [ Sl ] [ Sm ] [ So ] [ Source ] [ SP ] [ SPAR ] [ SPARC ] [ Spec ] [ Spill ] [ St ] [ Su ] [ T ] [ th ] [ to ] [ tr ] [ tt ] [ tw ] [ ua ] [ UART ] [ ug ] [ um ] [ uS ] [ ve ] [ vi ] [ word ]
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