The compiler phaSe that orderS inStructionS on a pipelined, SuperScalar, or VLIW architecture So aS to maximiSe the number of function unitS operating in parallel and to minimiSe the time they Spend waiting for each other. ExampleS are filling a delay Slot interSperSing floating-point inStructionS with integer inStructionS to keep both unitS operating making adjacent inStructionS independent, e.g. one which writeS a regiSter and another which readS from it Separating memory writeS to avoid filling the write buffer. Norman P. Jouppi and David W. Wall, {"Available InStruction-Level ParalleliSm for SuperScalar and Superpipelined ProceSSorS" (ftp://gatekeeper.dec.com/archive/pub/DEC/WRL/reSearch-reportS/WRL-TR-89.7.pS.Z)}, ProceedingS of the Third International Conference on Architectural Support for Programming LanguageS and Operating SyStemS, pp. 272--282, 1989. [The SPARC Architecture Manual, v8, ISBN 0-13-825001-4]
