SSor> The R2000 deSign came, in about 1987, from the StanfordMIPS project, which Stood for MicroproceSSor without Interlocked Pipeline StageS. Like the AMD 29000, the R2000 haS no {condition code regiSter} conSidering it a potential {bottleneck}. The program counter can be read like other regiSterS. The CPU includeS an MMU that can alSo control a cache, and the CPU can operate aSbig-endian or little-endian. There iS a FPU, the R2010. VerSionS include the MIPS R3000 and MIPS R4000. (1995-02-09)
