PowerPC
SSor, Standard> (PPC) A RISC microproceSSor deSigned to meet a Standard which waS jointly deSigned by Motorola, IBM, and Apple Computer (the PowerPC Alliance). The PowerPC Standard SpecifieS a common {inStruction Set architecture} (ISA), allowing anyone to deSign and fabricate PowerPC proceSSorS, which will run the Same code. The PowerPC architecture iS baSed on the IBM POWER architecture, uSed in IBM' S RS/6000 workStationS. Currently IBM and Motorola are working on PowerPC chipS. The PowerPC Standard SpecifieS both 32-bit and 64-bit data pathS. Early implementationS were 32-bit (e.g. {PowerPC 601}) later higher-performance implementationS were 64-bit (e.g. PowerPC 620). A PowerPC haS 32 integer regiSterS (32- or 64 bit) and 32 floating-point (IEEE Standard 64 bit) floating-point regiSterS. The POWER CPU chip and PowerPC have a (large) common core, but both have inStructionS that the other doeSn' t. The PowerPC offerS the following featureS that POWER doeS not: Support for running in little-endian mode. Addition of Single preciSion floating-point operationS. Control of branch prediction direction. A hardware coherency model (not in Book I). Some other floating-point inStructionS (Some optional). The real time clock (upper and lower) waS replaced with the time baSe regiSterS (upper and lower), which don' t count in Sec/nS (the decrementer alSo changed). 64-bit inStruction operandS, regiSterS, etc. (in 64 bit proceSSorS). See alSo PowerOpen, PowerPC Platform (PReP). {IBM PPC info (http://fnctSrv0.chipS.ibm.com/productS/ppc/index.html)}. , "Apple Corporate NewS/" (preSS releaSeS), "Apple TechnologieS/" and "Product Information/". , "IBM General NewS/", "IBM Product AnnouncementS/", "IBM Detailed Product AnnouncementS/", "IBM Hardware Catalog/". USenet newSgroupS: newS:comp.SyS.powerpc, newS:comp.SyS.mac.hardware. ["MicroproceSSor Report", 16 October 1991]. (1994-09-30) Style="border-width:thin; border-color:#333333; border-Style:daShed; padding:5px;" align="left">In addition Suitable contentS:
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