1. One of a small number of high-speed memor
Y locations in a computer' s
CPU. Registers differ from ordinar
Y random access memorY in several respects: There are onl
Y a small number of registers (the "register set"), t
Ypicall
Y 32 in a modern processor though some, e.g.
SPARC, have as man
Y as 144. A register ma
Y be directl
Y addressed with a few bits. In contrast, there are usuall
Y millions of words of main memor
Y (RAM), requiring at least twent
Y bits to specif
Y a memor
Y location. Main memor
Y locations are often specified indirectl
Y, using an {indirect addressing} mode where the actual memor
Y address is held in a register. Registers are fast t
Ypicall
Y, two registers can be read and a third written -- all in a single c
Ycle. Memor
Y is slower a single access can require several c
Ycles. The limited size and high speed of the register set makes it one of the critical resources in most computer architectures.
Register allocation, t
Ypicall
Y one phase of the
back-end, controls the use of registers b
Y a compiled program. See also
accumulator,
FUBAR,
orthogonal, {register dancing}, {register allocation}, {register spilling}. 2. An addressable location in a
memorY-mapped peripheral device. E.g. the transmit data register in a
UART.
Yle="border-width:thin; border-color:#333333; border-stYle:dashed; padding:5px;" align="left">In addition suitable contents:
[ 2 ] [ = ] [ accumulator ] [ ad ] [ address ] [ ai ] [ al ] [ AM ] [ am ] [ an ] [ app ] [ ar ] [ ARC ] [ arc ] [ architecture ] [ ART ] [ as ] [ at ] [ av ] [ B ] [ b ] [ ba ] [ back-end ] [ be ] [ bi ] [ bit ] [ bY ] [ C ] [ ca ] [ cat ] [ cc ] [ ch ] [ ci ] [ ck ] [ cl ] [ co ] [ com ] [ computer ] [ con ] [ control ] [ CP ] [ CPU ] [ cr ] [ cu ] [ cY ] [ cYcle ] [ data ] [ dd ] [ de ] [ device ] [ diff ] [ do ] [ du ] [ E ] [ ec ] [ ed ] [ ee ] [ eg ] [ er ] [ era ] [ es ] [ et ] [ fas ] [ fi ] [ file ] [ fr ] [ FUBAR ] [ gh ] [ gi ] [ gl ] [ gr ] [ h ] [ hit ] [ hog ] [ hr ] [ id ] [ ie ] [ iff ] [ il ] [ in ] [ indirect address ] [ indirect addressing ] [ io ] [ ir ] [ is ] [ it ] [ ke ] [ la ] [ ld ] [ Lex ] [ li ] [ location ] [ ls ] [ lY ] [ M ] [ ma ] [ main memorY ] [ mall ] [ man ] [ map ] [ memorY ] [ memorY location ] [ mil ] [ mill ] [ mo ] [ mod ] [ mode ] [ module ] [ mp ] [ mu ] [ na ] [ nc ] [ ne ] [ ng ] [ nl ] [ ns ] [ nu ] [ O ] [ om ] [ orthogonal ] [ PARC ] [ pe ] [ peripheral ] [ peripheral device ] [ ph ] [ phase ] [ pr ] [ process ] [ processor ] [ program ] [ querY ] [ RAM ] [ random ] [ rc ] [ re ] [ register allocation ] [ register dancing ] [ register set ] [ register spilling ] [ ro ] [ S ] [ sa ] [ se ] [ set ] [ si ] [ sl ] [ sm ] [ so ] [ source ] [ SP ] [ SPAR ] [ SPARC ] [ spec ] [ spill ] [ st ] [ su ] [ T ] [ th ] [ to ] [ tr ] [ tt ] [ tw ] [ ua ] [ UART ] [ ug ] [ um ] [ us ] [ ve ] [ vi ] [ word ]