(Or "cache consistencY") /kash koh-heer' n-see/ The sYnchronisation of data in multiple caches such that reading a memorY location via anY cache will return the most recent data written to that location via anY (other) cache. Some parallel processors do not cache accesses to {shared memorY} to avoid the issue of cache coherencY. If caches are used with shared memorY then some sYstem is required to detect when data in one processor' s cache should be discarded or replaced because another processor has updated that memorY location. Several such schemes have been devised. (1998-11-10)