register
1. One of a small number of high-speed memory locations in a computer' s CPU. R egisters differ from ordinary random access memory in several respects: There are only a small number of r egisters (the "r egister set"), typically 32 in a modern processor though some, e.g. SPARC, have as many as 144. A r egister may be directly addressed with a few bits. In contrast, there are usually millions of words of main memory (RAM), requiring at least twenty bits to specify a memory location. Main memory locations are often specified indirectly, using an {indirect addressing} mode where the actual memory address is held in a r egister. R egisters are fast typically, two r egisters can be read and a third written -- all in a single cycle. Memory is slower a single access can require several cycles. The limited size and high speed of the r egister set makes it one of the critical resources in most computer architectures. Register allocation, typically one phase of the back-end, controls the use of r egisters by a compiled program. See also accumulator, FUBAR, orthogonal, {r egister dancing}, {r egister allocation}, {r egister spilling}. 2. An addressable location in a memory-mapped peripheral device. E.g. the transmit data r egister in a UART. In addition suitable contents: [ 2 ] [ = ] [ accumulator ] [ ad ] [ address ] [ ai ] [ al ] [ AM ] [ am ] [ an ] [ app ] [ ar ] [ ARC ] [ arc ] [ architecture ] [ ART ] [ as ] [ at ] [ av ] [ B ] [ b ] [ ba ] [ back-end ] [ be ] [ bi ] [ bit ] [ by ] [ C ] [ ca ] [ cat ] [ cc ] [ ch ] [ ci ] [ ck ] [ cl ] [ co ] [ com ] [ computer ] [ con ] [ control ] [ CP ] [ CPU ] [ cr ] [ cu ] [ cy ] [ cycle ] [ data ] [ dd ] [ de ] [ device ] [ diff ] [ do ] [ du ] [ E ] [ ec ] [ ed ] [ ee ] [ eg ] [ er ] [ era ] [ es ] [ et ] [ fas ] [ fi ] [ file ] [ fr ] [ FUBAR ] [ gh ] [ gi ] [ gl ] [ gr ] [ h ] [ hit ] [ hog ] [ hr ] [ id ] [ ie ] [ iff ] [ il ] [ in ] [ indirect address ] [ indirect addressing ] [ io ] [ ir ] [ is ] [ it ] [ ke ] [ la ] [ ld ] [ Lex ] [ li ] [ location ] [ ls ] [ ly ] [ M ] [ ma ] [ main memory ] [ mall ] [ man ] [ map ] [ memory ] [ memory location ] [ mil ] [ mill ] [ mo ] [ mod ] [ mode ] [ module ] [ mp ] [ mu ] [ na ] [ nc ] [ ne ] [ ng ] [ nl ] [ ns ] [ nu ] [ O ] [ om ] [ orthogonal ] [ PARC ] [ pe ] [ peripheral ] [ peripheral device ] [ ph ] [ phase ] [ pr ] [ process ] [ processor ] [ program ] [ query ] [ RAM ] [ random ] [ rc ] [ re ] [ register allocation ] [ register dancing ] [ register set ] [ register spilling ] [ ro ] [ S ] [ sa ] [ se ] [ set ] [ si ] [ sl ] [ sm ] [ so ] [ source ] [ SP ] [ SPAR ] [ SPARC ] [ spec ] [ spill ] [ st ] [ su ] [ T ] [ th ] [ to ] [ tr ] [ tt ] [ tw ] [ ua ] [ UART ] [ ug ] [ um ] [ us ] [ ve ] [ vi ] [ word ]
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