An interrupt caused by a specific machine language operation code (e.g. the Motorola 68000' s TRAP, the {IBM System/390}' s SVC or the {ARM}' s SWI) rather than by a hardware event. As with a hardware interrupt, this causes the processor to store the current state, store identifying information about the particular interrupt, and pass control to a first level interrupt handler. A trap is similar except that it is caused by an unexpected software condition or error (e.g. divide by zero, undefined instruction) rather than a deliberate instruction. (1995-02-14)

In addition suitable contents:
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