(circuit design) (LSSD) A kind of scan design which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held low during system operation but cause the scan data to be latched when pulsed high during scan. ____ | | Sin ----|S | A ------|> | | Q|---+--------------- Q1 D1 -----|D | | CLK1 ---|> | | |____| | ____ | | | +---|S | B -------------------|> | | Q|------ Q2 / SOut D2 ------------------|D | CLK2 ----------------|> | |____| In a single latch LSSD configuration, the second latch is used only for scan operation. Allowing it to be use as a second system latch reduces the silicon overhead. (1995-02-15)

In addition suitable contents:
[ 2 ] [ = ] [ ad ] [ ai ] [ al ] [ am ] [ an ] [ app ] [ ar ] [ arc ] [ as ] [ at ] [ au ] [ av ] [ B ] [ b ] [ be ] [ C ] [ ca ] [ ch ] [ ci ] [ circuit ] [ ck ] [ CL ] [ cl ] [ clock ] [ co ] [ con ] [ cu ] [ D ] [ data ] [ de ] [ design ] [ du ] [ ec ] [ ed ] [ edu ] [ ee ] [ er ] [ era ] [ es ] [ et ] [ fi ] [ file ] [ fo ] [ for ] [ gh ] [ gl ] [ gn ] [ gu ] [ h ] [ hr ] [ icon ] [ id ] [ il ] [ in ] [ input ] [ io ] [ ir ] [ is ] [ it ] [ K ] [ ki ] [ la ] [ latch ] [ ld ] [ Lex ] [ li ] [ ls ] [ LSSD ] [ ly ] [ ma ] [ master ] [ mo ] [ mod ] [ mode ] [ module ] [ na ] [ ne ] [ nf ] [ ng ] [ nl ] [ no ] [ norm ] [ np ] [ O ] [ op ] [ output ] [ overhead ] [ pa ] [ pe ] [ ph ] [ ping ] [ Q ] [ query ] [ rc ] [ re ] [ rl ] [ S ] [ sc ] [ scan ] [ scan design ] [ SD ] [ se ] [ sh ] [ si ] [ sig ] [ silicon ] [ sl ] [ SO ] [ st ] [ sy ] [ system ] [ ] [ tc ] [ test ] [ th ] [ to ] [ tp ] [ tw ] [ us ] [ ve ] [ win ]