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Internes

Lexikon


MESI protocol


Modified, Exclusive, Shared, Invalid. A cache coherency protocol where each cache line is marked with one of the four states. The MESI protocol is used by the Pentium processor. (1995-05-05)

In addition suitable contents:
[ = ] [ al ] [ am ] [ ar ] [ arc ] [ at ] [ b ] [ by ] [ ca ] [ cache ] [ cache coherency ] [ cache line ] [ ch ] [ cl ] [ co ] [ cy ] [ du ] [ E ] [ ed ] [ er ] [ es ] [ ESI ] [ fi ] [ file ] [ fo ] [ h ] [ hr ] [ id ] [ ie ] [ il ] [ in ] [ is ] [ it ] [ ke ] [ Lex ] [ li ] [ line ] [ lu ] [ M ] [ ma ] [ mo ] [ mod ] [ module ] [ na ] [ nc ] [ ne ] [ Pentium ] [ ph ] [ pr ] [ process ] [ processor ] [ protocol ] [ query ] [ rc ] [ re ] [ ro ] [ S ] [ se ] [ SI ] [ si ] [ so ] [ st ] [ state ] [ T ] [ th ] [ to ] [ um ] [ us ] [ va ] [ ve ]






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