A cache with a posted write-through policy (e.g. Intel 80386) delays the write-back to main memory until the bus is not in use.

In addition suitable contents:
[ 386 ] [ 80386 ] [ = ] [ ai ] [ am ] [ ar ] [ arc ] [ b ] [ ba ] [ bus ] [ ca ] [ cache ] [ ch ] [ ck ] [ cy ] [ de ] [ du ] [ ed ] [ er ] [ fi ] [ file ] [ gh ] [ h ] [ hr ] [ id ] [ il ] [ in ] [ Intel 80386 ] [ is ] [ it ] [ la ] [ Lex ] [ li ] [ ma ] [ main memory ] [ memory ] [ mo ] [ mod ] [ module ] [ na ] [ no ] [ ph ] [ post ] [ query ] [ rc ] [ re ] [ ro ] [ se ] [ st ] [ th ] [ to ] [ ug ] [ us ] [ write ] [ write-back ] [ write-through ]