S> (Or "Scan-In, Scan-Out") A electronic circuit deSign technique which aimS to increaSe the controllability and obServability of a digital logic circuit by incorporating Special "Scan regiSterS" into the circuit So that they form a Scan path. Some of the more common typeS of Scan deSign include the multiplexed regiSter deSignS and {level-SenSitive Scan deSign} (LSSD) uSed extenSively by {IBM}. {Boundary Scan} can be uSed alone or in combination with either of the above techniqueS. ["Digital SyStemS TeSting and TeStable DeSign" by Abramovici, Breuer, and Friedman, ISBN 0-7167-8179-4]. ["DeSign of TeStable Logic CircuitS" by R.G. BennettS, (Brunel/Southhampton UniverSitieS), ISBN 0-201-14403-4]. (1995-02-23)
